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LV XVHG DV WKH UHFHLYHU UHIHUHQFH FORFNi 7KH WUDQVFHLYHU FDQ DOVR EH UHVHW IURP WKH +RVW RU +DUG ZDUH 0RGHi ,Q +RVW 0RGHn UHVHW LV FRPPDQGHG E\ VLPXO WDQHRXVO\ ZULWLQJ RQHV WR 5/223 DQG //223n DQG D ]HUR WR 7$26i ,Q +DUGZDUH 0RGHn UHVHW LV FRPPDQGHG E\ KROGLQJ 5/223 DQG //223 +LJK VLPXOWDQHRXVO\ IRU eii QV ZKLOH KROGLQJ 7$26 /RZi ,Q HLWKHU PRGHn UHVHW FOHDUV DQG VHWV DOO UHJLVWHUV WR ii )81&7,21$/ '(6&5,37,21 7KH /;7eii LV D IXOO\ LQWHJUDWHG 3&0 WUDQVFHLYHU IRU iieee 0ESV o7io DSSOLFDWLRQVi ,W DOORZV IXOOGXSOH[ WUDQV PLVVLRQ RI GLJLWDO GDWD RYHU H[LVWLQJ WZLVWHGSDLU LQVWDOOD WLRQVi 7KH /;7eii LQWHUIDFHV ZLWK WZR WZLVWHGSDLU OLQHV oRQH SDLU IRU WUDQVPLWn RQH SDLU IRU UHFHLYHo WKURXJK VWDQGDUG SXOVH WUDQVIRUPHUV DQG DSSURSULDWH UHVLVWRUVi The figure on the front page of this section is a block diagram of the LXT310. The transceiver may be controlled by a microprocessor through the serial port (Host Mode), or by individual pin settings (Hardware Mode). The jitter attenuator may be positioned in either the transmit or receive path. 5HFHLYHU The twisted-pair input is received via a 1:1 transformer. Recovered data is output at RPOS/RNEG (RDATA in unipolar mode), and the recovered clock is output at RCLK. Refer to Test Specifications for receiver timing. The signal received at RPOS and RNEG is processed through the receive equalizer. The Equalizer Gain Limit (EGL) input determines the maximum gain that may be applied at the equalizer. When set Low, up to 36 dB of gain may be applied. :KHQ (*/ LV +LJKn JDLQ LV OLPLWHG WR QR PRUH WKDQ ec G% SURYLGLQJ IRU LQFUHDVHG QRLVH PDUJLQ LQ VKRUWHU ORRS RSHU DWLRQi ,QVHUWLRQ ORVV RI WKH OLQH LQ aeie G% VWHSVn DV LQGLFDWHG E\ WKH UHFHLYH HTXDOL]HU VHWWLQJn LV HQFRGHG LQ WKH /$71 RXWSXW DV VKRZQ LQ )LJXUH ei 3RZHU 5HTXLUHPHQWV The LXT310 is a low-power CMOS device. It operates from a single +5 V power supply which can be connected externally to both the transmitter and receiver. However, the two inputs must be within .3 V of each other, and decoupled to their respective grounds separately. Refer to Application Information for typical decoupling circuitry. Isolation between the transmit and receive circuits is provided internally. ,QLWLDOL]DWLRQ DQG 5HVHW 2SHUDWLRQV 8SRQ SRZHU XSn WKH WUDQVFHLYHU LV KHOG VWDWLF XQWLO WKH SRZHU VXSSO\ UHDFKHV DSSUR[LPDWHO\ e 9i 8SRQ FURVVLQJ )LJXUH ea /$71 3XOVH :LGWK (QFRGLQJ 5&/. /$71 i e e e e /$71 /$71 e 5&/.n i G% RI $WWHQXDWLRQ /$71 e 5&/.n eeie G% RI $WWHQXDWLRQ /$71 e 5&/.n ie G% RI $WWHQXDWLRQ i 5&/.n aeie G% RI $WWHQXDWLRQ 127(a /$71 LV VWDEOH DQG YDOLG RQ WKH ULVLQJ HGJH RI 5&/. L1 ee /;7eii 7i &68i,6'1 35, 7UDQVFHLYHU The equalized signal is filtered and applied to the peak detector and data slicers. The peak detector samples the inputs and determines the maximum value of the received signal. A percentage of the peak value is provided to the data slicers as a threshold level to ensure optimum signalto-noise ratio. The threshold is set to 50% of the peak value. The receiver is capable of accurately recovering signals with up to 36 dB of cable attenuation (from 2.4 V) After processing through the data slicers, the received signal is routed to the data and timing recovery section, then to the B8ZS decoder (if selected) and to the LOS processor. The LOS Processor loads a digital counter at the RCLK frequency. The count is incremented each time a zero (space) is received, and reset to zero each time a one (mark) is received. Upon receipt of 175 consecutive zeros the LOS pin goes High, and a smooth transition replaces the RCLK output with the MCLK. (During LOS if MCLK is not supplied and JASEL = 1, the RCLK output is replaced with the centered crystal clock.) Received marks will be output regardless of the LOS status, but the LOS pin will not reset until the ones density reaches 12.5 %. This level is based on receipt of at least 4 ones in any 32-bit period. 7KH WUDQVPLWWHG SXOVH VKDSH LV GHWHUPLQHG E\ /LQH %XLOG 2XW o/%2o LQSXWV /%2i DQG /%2e DV IROORZVa /LQH %XLOG2XW oG%o /%2i /%2e i i i aeie ie i i i i eeie i i LBO settings are input through the serial port in the Host Mode. In the Hardware Mode, LBO inputs are applied through individual pins. Shaped pulses meeting the various T1 CSU and ISDN PRI requirements are applied to the AMI line driver for transmission onto the line at TTIP and TRING. Refer to Test Specifications for T1 pulse mask specifications. 6KRUW &LUFXLW /LPLW 7KH /;7eii WUDQVPLWWHU LV HTXLSSHG ZLWK D VKRUWFLUFXLW OLPLWHUi 7KLV IHDWXUH OLPLWV WR DSSUR[LPDWHO\ iei P$ 506 WKH FXUUHQW WKH WUDQVPLWWHU ZLOO VRXUFH LQWR D ORZLPSHG DQFH ORDGi 7KH OLPLWHU WULSV ZKHQ WKH 506 FXUUHQW H[FHHGV WKH OLPLW IRU iii "V oa iei PDUNVoi ,W DXWRPDWLFDOO\ UHVHWV ZKHQ WKH ORDG FXUUHQW GURSV EHORZ WKH OLPLWi 7KH /;7eii PHHWV RU H[FHHGV )&& DQG $7/7 VSHFLILFD WLRQV IRU &68 DQG 1, DSSOLFDWLRQVn DV ZHOO DV $16, 7i(in DQG &&,77 UHTXLUHPHQWV IRU ,6'1 35,i 7UDQVPLWWHU Input data (bipolar or unipolar) for transmission onto the line is clocked serially into the device. Bipolar data is input at pin 3 (TPOS) and pin 4 (TNEG). Unipolar data is input at pin 3 (TDATA) only. (Unipolar mode is enabled by holding pin 4 high for 16 RCLK cycles). Input data may be passed through the Jitter Attenuator and/or B8ZS encoder, if selected. In Host Mode, B8ZS is selected by setting bit D3 of the input data byte. In Hardware Mode, B8ZS is selected by connecting the MODE pin to RCLK. Input synchronization is supplied by the transmit clock (TCLK). Timing requirements for TCLK and the Master Clock (MCLK) are defined in Test Specifications. /LQH &RGH The LXT310 transmits data as a 50% AMI line code as shown in Figure 3. Power consumption is reduced by activating the AMI line driver only to transmit a mark. The output driver is disabled during transmission of a space. Biasing of the transmit DC level is on-chip. )LJXUH ea eio $0, &RGLQJ %LW &HOO 77,3 i 75,1* i i ,GOH 0RGH 7KH /;7eii LQFRUSRUDWHV D WUDQVPLW LGOH PRGHi 7KLV DOORZV PXOWLSOH WUDQVFHLYHUV WR EH FRQQHFWHG WR D VLQJOH OLQH IRU UHGXQGDQW DSSOLFDWLRQVi 77,3 DQG 75,1* UHPDLQ LQ D KLJK LPSHGDQFH VWDWH ZKHQ 7&/. LV QRW SUHVHQW o7&/. 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With the exception of the INT and CLKE functions, Hardware Mode provides all the functions provided in the Host Mode. In the Hardware Mode RPOS/RNEG or RDATA outputs are valid on the rising edge of RCLK. The LXT310 operates in Hardware Mode only when MODE is set Low or connected to RCLK. ,Q 5HPRWH /RRSEDFN o5/223o 0RGHn WKH WUDQVPLW GDWD DQG FORFN LQSXWV o7&/. DQG 7326i71(* RU 7'$7$o DUH LJQRUHGn DQG WKH LQOLQH HQFRGHUV DQG GHFRGHUV DUH E\SDVVHGi 7KH 5326i51(* RU 5'$7$ RXWSXWV DUH ORRSHG EDFN WKURXJK WKH WUDQVPLW FLUFXLWV DQG RXWSXW RQ 77,3 DQG 75,1* DW WKH 5&/. IUH TXHQF\i 5HFHLYHU FLUFXLWV DUH XQDIIHFWHG E\ WKH 5/223 FRPPDQG DQG FRQWLQXH WR RXWSXW WKH 5&/. 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WR 5/223i 1/223 GHWHFWLRQ PD\ EH GLVDEOHG E\ UHVHWWLQJ WKH FKLSi /RFDO /RRSEDFN /RFDO /RRSEDFN o//223o LV GHVLJQHG WR H[HUFLVH WKH PD[LPXP QXPEHU RI IXQFWLRQDO EORFNVi 'XULQJ //223 RSHUDWLRQn WKH 57,3i55,1* LQSXWV IURP WKH :KHQ 1/223 GHWHFWLRQ LV HQDEOHGn WKH UHFHLYHU PRQ LWRUV WKH LQSXW GDWD VWUHDP IRU WKH 1/223 GDWD SDW WHUQV oiiiii HQDEOHn iii GLVDEOHoi :KHQ DQ 1/223 HQDEOH GDWD SDWWHUQ LV UHSHDWHG IRU D PLQLPXP RI ILYH VHFRQGV oZLWK iie %(5on WKH GHYLFH EHJLQV UHPRWH ORRSEDFN RSHUDWLRQi 7KH /;7eii UHVSRQGV WR ERWK IUDPHG DQG XQIUDPHG 1/223 SDWWHUQVi 2QFH UHPRWH QHWZRUN ORRSEDFN GHWHFWLRQ LV HQDEOHG DW WKH FKLS DQG DFWLYDWHG E\ WKH FRUUHFW GDWD SDWWHUQn LW LV LGHQWLFDO WR UHPRWH ORRSEDFN LQLWLDWHG DW WKH FKLSi 1/223 LV UHVHW E\ UHFHLYLQJ WKH GLVDEOH SDWWHUQ IRU e VHFRQGVn RU E\ DFWLYDWLRQ RI 5/223i 1/223 LV WHP SRUDULO\ LQWHUUXSWHG E\ //223n EXW WKH 1/223 VWDWH LV QRW UHVHWi ea L1 $SSOLFDWLRQ ,QIRUPDWLRQ $33/,&$7,21 ,1)250$7,21 )LJXUH ea 7\SLFDO /$71 'HFRGLQJ &LUFXLW 9FF &, 5&/. /$71 4 ' 4 ' &2 4 5 &, &2 4 5 /$71 'HFRGLQJ &LUFXLWV DQG ([WHUQDO &RPSRQHQWV To conserve pins, the line attenuation output is encoded as a simple serial bit stream. Table 4 provides the decoded output for each equalizer setting. Figure 5 is a typical decoding circuit for the LATN output. It uses a 2-bit synchronous counter (half of a 4-bit counter) with synchronous reset, and a pair of flip-flops. Table 5 lists approved crystals and transformers. 7DEOH ea /$71 2XWSXW &RGLQJ /i i i i i /e i i i i /LQH $WWHQXDWLRQ iii G% aeie G% ieii G% eeie G% /i /e 7DEOH ea $SSURYHG &U\VWDOV DQG 7UDQVIRUPHUV &RPSRQHQW &U\VWDO ociiaec 0+]o 0DQXIDFWXUHU 3DUW 1XPEHUV 03i eaiaiii i eieeiie 06&ieiiii% ciaeciai 9)ea$ic)1i 8iaiaciaec63 ieeeeiic,& cc=ieia caeieaee ceeein ceaeaei caeieaeeaei DQG caeieiaei 7'ciieie* DQG 7'caeieie* oFRPER 7[i5[o )( aiiciee caeieaeae ceaec DQG ceaeaea caeieiaei DQG caeiiaeii 7'ciieie* DQG 7'caeieie* oFRPER 7[i5[o 07URQ 0RQLWRU 3URGXFWV &76 .QLJKWV 9DOSH\ )LVKHU 8i6i &U\VWDO 7[ 7UDQVIRUPHU %HOO )XVH oiaeo )(( )LO0DJ 0LGFRP 3XOVH (QJLQHHULQJ 6FKRWW &RUS +$/2 5[ 7UDQIRUPHU )(( )LO0DJ oiaio 0LGFRP 3XOVH (QJLQHHULQJ 6FKRWW &RUS +$/2 L1 ea /;7eii 7i &68i,6'1 35, 7UDQVFHLYHU +RVW 0RGH $SSOLFDWLRQV )LJXUH c VKRZV D W\SLFDO 7i &68 DSSOLFDWLRQ ZLWK WKH /;7eii RSHUDWLQJ LQ WKH +RVW 0RGH o02'( SLQ WLHG KLJKoi $ 7ii(6) )UDPHU SURYLGHV WKH GLJLWDO LQWHUIDFH ZLWK WKH KRVW FRQWUROOHUi %RWK GHYLFHV DUH FRQWUROOHG WKURXJK WKH VHULDO LQWHUIDFHi ,Q WKH +RVW 0RGHn WKH /26 DODUP LV UHSRUWHG YLD WKH VHULDO SRUW VR WKH /26 SLQ LV DOORZHG WR IORDWi $Q /;3cii$ &ORFN $GDSWHU o&/$'o SURYLGHV WKH eiiea 0+] V\VWHP EDFNSODQH FORFNn ORFNHG WR WKH UHFRYHUHG 7DEOH ca /;7eii &U\VWDO 6SHFLILFDWLRQV o([WHUQDOo 3DUDPHWHU )UHTXHQF\ )UHTXHQF\ VWDELOLW\ iieee 0+] FORFN VLJQDOi 7KH ciiaec 0+] FU\VWDO DFURVV ;7$/,1 DQG ;7$/287 HQDEOHV WKH -$/ ZKLFK LV VZLWFKHG WR WKH WUDQVPLW VLGH E\ WKH JURXQG RQ -$6(/i o5HIHU WR 7DEOH e IRU DSSURYHG FU\VWDOV DQG WUDQVIRUPHUVio 7KH SRZHU VXSSO\ LQSXWV DUH WLHG WR D FRPPRQ EXV ZLWK DSSURSULDWH GHFRXSOLQJ FDSDFLWRUV oca ") DQG iii ")o LQVWDOOHG RQ HDFK VLGHi 7KH WZLVWHGSDLU LQWHUIDFHV DUH UHODWLYHO\ VLPSOHi $ iii UHVLVWRU DFURVV WKH LQSXW RI D iai WUDQVIRUPHU LV XVHG RQ WKH UHFHLYH VLGHn DQG D SDLU RI ieie UHVLVWRUV DUH LQVWDOOHG LQ OLQH ZLWK WKH iae RXWSXW WUDQVIRUPHUi 6SHFLILFDWLRQ ciiaec 0+] ` ei SSP # ee & ` ee SSP IURP ei & WR ae & o5HI ee & UHDGLQJo &/ ii S) WR iaiae S)n o) iaee WR iae SSP &/ iaiae S) WR ee S)n ) iaee WR iae SSP ei 0D[LPXP $7 3DUDOOHO eii P: )XQGDPHQWDO +&ea o5e:on &2 ae S) PD[LPXP &0 iae I) W\SLFDO 3XOODELOLW\ (IIHFWLYH VHULHV UHVLVWDQFH &U\VWDO FXW 5HVRQDQFH 0D[LPXP GULYH OHYHO 0RGH RI RSHUDWLRQ &U\VWDO KROGHU eii L1 $SSOLFDWLRQ ,QIRUPDWLRQ )LJXUH ca 7\SLFDO /;7eii +RVW 0RGH 7ii&68 $SSOLFDWLRQ 7R +RVW &RQWUROOHU 7ii(6) )5$0(5 706<1& )6<1& CS 6'2 6', INT 6&/. 7&/. 7326 71(* 636 51(* 5326 1RWH i 5&/. iieee 0+] 9o iieee 0+] /;7eii 75$16&(,9(5 0&/. 7&/. 7326 71(* 02'( 51(* 5326 5&/. ;7$/,1 &/.( 6&/. CS 6'2 6', INT 5*1' 59o 55,1* 57,3 /$71 (*/ 75,1* 79o 9o ieie ieie iae iieee 0+] 7i /LQH 7UDQVPLW 9o ee N i9 iii ) iai iii 7i /LQH 5HFHLYH /;3cii$ &/$' &/., &/.2 eiiea 0+] FSI ciiaec 0+] ;7$/287 -$6(/ /26 77,3 6HH )LJXUH e 127( i 7KH /;7eii LV FRPSDWLEOH ZLWK D ZLGH YDULHW\ RI IUDPLQJiVLJQDOLQJ GHYLFHVi 7*1' iii ) ca ) L1 eii /;7eii 7i &68i,6'1 35, 7UDQVFHLYHU /;7eii +DUGZDUH 0RGH $SSOLFDWLRQV Figure 7 is a typical 1.544 Mbps ISDN PRI application with the LXT310, a T1/ESF framer and an LXP600A clock adapter. The LXT310 is operating in the Hardware Mode with B8ZS encoding enabled (MODE pin 5 tied to RCLK). As in the T1/CSU application, Figure 6, this configuration is illustrated with a single power supply bus. CMOS control logic is used to set both LBO pins high, selecting the 22.5 dB LBO, and the EGL pin is tied low, allowing for full receiver gain. The TAOS, LLOOP and RLOOP diagnostic modes are individually controllable. The RCLK input to the OR gate at RLOOP allows for clocking of the RLOOP pin, which enables network loopback detection. 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Price & Availability of LXT310
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